1. Field of the Invention
The present invention relates to a method of forming local oxidation isolation structures in semiconductor and/or integrated circuit devices and, more particularly, to a method of forming such isolation structures that reduces stress-related defects and that results in a significantly less field oxide "thinning".
2. Discussion of the Background
Integrated circuits (ICs) have electric circuits which comprise a number of isolated devices, e.g., transistors, interconnected through one or more conducting paths. To fabricate ICs, individual devices must be created in a silicon substrate in such a way that they are electrically isolated from one another. Isolation of individual devices ensures that the state (e.g., on or off) and conductance of the individual devices are independently controlled. Without proper isolation, leakage currents may occur, causing power dissipation, noise margin degradation and/or voltage shifts on dynamic nodes. In CMOS circuits, leakage current may lead to device latch up, which can damage the integrated circuit. Further, without proper isolation, cross-talk between devices may occur, thereby disturbing the logic state of a logic gate which is made up of a number of the individual devices.
Integrated circuit designers face other challenges that may conflict with the desire for proper isolation. For example, it is commercially important to make the spacing between individual components or devices as small as possible to enable an increase in device density (e.g., number of devices per unit area). Furthermore, there is also a strong desire in the art to ensure that the fabrication processes which are used to produce the isolation structures are simple to implement and control. At the same time, these processes should not adversely impact the characteristics of active areas of the semiconductor die which will form the integrated circuit.
To meet these and other challenges in manufacturing semiconductor devices, Local Oxidation of Silicon (LOCOS) has become a widely used processing step in forming lateral isolation structures between devices (e.g., transistors) on a semiconductor die. Indeed, the LOCOS process has become the "work horse" isolation technology for MOS devices down to about 0.5 .mu.m geometries. LOCOS processes are popular, in part, because they produce a fairly planar surface which is highly desirable for resolving and patterning dense features on a semiconductor die.
FIG. 1 illustrates a semiconductor die 10 at one stage of a conventional LOCOS process. A thin layer of a pad oxide 14 of approximately 10 to 50 nm thickness is formed on the surface of a silicon substrate 12. Next, a thicker layer of silicon nitride 16 is deposited on the pad oxide layer 14. The silicon nitride layer 16 may be approximately 100 to 150 nm thick and may be deposited using conventional chemical vapor deposition (CVD) techniques.
In the resulting structure, the pad oxide layer 14 is used to cushion the transition of stresses between the silicon substrate 12 and the nitride layer 16. Such stresses may occur in the nitride layer 16 due to various effects, including: (1) a mismatch between the thermal coefficients of expansion of the nitride layer 16 and the silicon substrate 12; and (2) a tendency of the growing field oxide (see below) to lift the edges of the nitride layer 16. Such stresses may cause the nitride layer 16 to crack as the field oxide layer is grown, thus defeating the purpose of the nitride layer 16 as an oxidation barrier.
Stresses may also be transmitted from the nitride layer 16 to the silicon substrate 12. These stresses may produce defects in the silicon crystal. In general, the thicker the pad oxide layer 14, the fewer the defects in both the nitride layer 16 and the silicon substrate 12 during the field oxide layer growth. However, a thick pad oxide layer 14 may render the nitride layer 16 less effective as an oxidation mask by allowing lateral oxidation to take place. Consequently, the thinnest pad oxide layer 14 that effectively relieves stress is generally employed.
After the nitride layer 16 is deposited, it may be patterned, for example by using conventional photolithography techniques wherein a photoresist layer (not shown) is spun on and exposed through a mask. As shown in FIG. 2, the nitride layer 16 and pad oxide layer 14 may then be etched to expose a top surface of the silicon substrate 12 in a region 18 that will become an isolation structure. In other words, the nitride layer 16 and pad oxide layer 14 are patterned so that after the etch they remain only over what will become the active regions in the silicon substrate 12.
With the region 18 still exposed, the silicon substrate 12 is oxidized to form a field oxide region 20 of desired thickness. The result is shown in FIG. 3 where a field oxide region 20 has been grown over silicon substrate 12. Even though this oxide grows mainly in areas where the silicon nitride layer 16 is absent, the oxide generally grows by diffusion, resulting in both vertical growth in the isolation region and lateral growth under the nitride and pad oxide layers 16 and 14. This lateral growth of the field oxide results in a so-called "bird's beak" because the shape of the oxide grown under the nitride resembles that of a bird's beak. Because it is the beak-to-beak distance "X" (see FIG. 7), over the silicon substrate 12 which will define the active transistor area, the smaller the bird's beak, the closer the devices (e.g., transistors) can be packed onto a given substrate. In other words, bird's beak encroachment leads to active areas that are narrower than originally patterned and isolation regions which are wider than originally patterned. What is desired is as small a bird's beak as possible, while maintaining electrical isolation between active areas.
A fundamental limitation of the LOCOS scheme is the "thinning" of the field oxide in narrow regions. This thinning occurs due to the high stresses generated during the growth of the oxide in narrow openings. It results in a significantly thinner oxide growth in narrow areas (0.5 .mu.m or less) as compared to wide areas (&gt;2 .mu.m). The thinning effect becomes more severe as the width of the narrow region decreases. The thinning of the field oxide gives rise to reduction in field threshold voltages which degrades the isolation between adjacent devices. Thinning effects provide for a field oxide having greater dimensions than a field oxide which does not display thinning, without a significant increase in the electrical insulating properties of the field oxide. The result is a lose of "real estate" since the increased dimensions of the field oxide are without substantial increase in the electrical isolation of active areas.
Another drawback of conventional LOCOS is that it is susceptible to defects caused by the high stresses generated in the narrow active areas, underneath the nitride layer, during field oxidation. There are also defects caused by the KOOI effect. These defects can degrade the gate oxide quality and transistor performance. Defect generation is enhanced as the geometries shrink and the bird's beak encroachment becomes a more significant portion of the field oxide surface area. What is desired, therefore, is a means of forming an isolation region in a semiconductor substrate that does not have the drawbacks and shortcomings of conventional methods and/or known variations thereof, and that is useful for isolating integrated circuits devices (e.g. transistors) having a geometry (e.g. gate width) of 0.35 .mu.m or less.